Conventionally, a data transfer has been carried out between memory chips or between memory circuits in synchronism with a clock signal. Therefore, when a clock frequency is slow, the transfer of all data becomes very slow. In order to transfer all data at a high speed when the clock frequency is slow, it is necessary to extremely increase the number of lines for connecting between the memories.
However, the increasing the number of lines for connecting between the memories leads to an increase in the size of a wiring area, which is not preferable. Therefore, when the clock frequency is slow, there may be considered a method of transferring data in synchronism with a high-speed clock signal by generating this high-speed clock using a PLL. However, the provision of the PLL has a problem of making complex the circuit, although it is not necessary to increase the number of lines in this case.